/**
  ******************************************************************************
  * @file    Libraries/Device/TS32F020D/TS32F020D_LL_Driver/inc/ts32f020d_ll_adc.h
  * @author  JUSHENG Application Team
  * @version V1.0.0
  * @date    02-19-2022
  * @brief   This file contains all the ADC LL firmware functions.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2022 JUSHENG</center></h2>
  *
  *
  *
  ******************************************************************************
  */ 
  
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TS32F020D_LL_ADC_H
#define __TS32F020D_LL_ADC_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "ts32f020d.h"
#include "ts32f020d_system.h"
     
/** @addtogroup TS32F020D_StdPeriph_Driver TS32F020D Driver
  * @{
  */
     
/** @addtogroup adc_interface_gr ADC Driver
  * @ingroup  TS32F020D_StdPeriph_Driver
  * @{
  */ 

/** @addtogroup ADC_LL_Driver ADC LL Driver
  * @ingroup  adc_interface_gr
  * @brief Mainly the driver part of the ADC module, which includes \b ADC \b Register 
  * \b Constants, \b ADC \b Exported \b Constants, \b ADC \b Exported \b Struct, \b ADC
  * \b Data \b transfers \b functions, \b ADC \b Initialization \b and \b ADC \b Configuration 
  * \b And \b Interrupt \b Handle \b function.
  * @{
  */

/* Exported types ------------------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/

/** @defgroup ADC_LL_Register_Constants ADC LL Register Constants
  * @ingroup  ADC_LL_Driver
  * @brief    ADC LL register constant table definition
  *
  *
@verbatim   
  ===============================================================================
                                Register Constants
  ===============================================================================  
  
    Register Constants mainly encapsulates each bit in each group in the ADC 
    register. In the process of configuration, the macro definition can be directly 
    called to configure the ADC register, mainly for convenience. Understand the 
    configuration of the ADC.
    
@endverbatim
  *
  * @{
  */

/***** ADC_CFG Register *****/
/*! RW, ADC ldo enable  
 */
#define LL_ADC_CFG_LDO_EN                                     (1UL << 19)

/*! RW, The interval time period between two consecutive samples (n*ADCCLK)
 */
#define LL_ADC_CFG_D2DCYC(n)                                  (((n)&0xF) << 13)

/*! RW, ADC prescale mask
 */
#define LL_ADC_CFG_PSC_MASK                                   (0x3F << 4)

/*! RW, ADC prescale  
 * 0  : 2 prescaler  
 * other : ( n + 1) prescaler  
 */
#define LL_ADC_CFG_PSC(n)                                     (((n)&0x3F) << 4)

/*! RW, ADC reference voltage selection
 * 00: 2V  
 * 01: 2.5V  
 * 10: 4.5V  
 * 11: AVCC  
 */
#define LL_ADC_CFG_REF_VOLTAGE_SEL(n)                         (((n)&0x3) << 2)

/*! RW, ADC supply voltage selection, Used to distinguish the selected offset parameter
 * 0: 5V Power  
 * 1: 3.3V Power  
 */
#define LL_ADC_CFG_VOLTAGE_SEL                            (1UL << 1)

/*! RW, ADC enabled
 */
#define LL_ADC_CFG_EN                                     (1UL << 0)


/***** ADC_CR Register *****/
/*! RW, Hardware data calibrate enable
 */
#define LL_ADC_CR_CAL_EN                                  (1UL << 28)

/*! WO, Software reset module internal state
 */
#define LL_ADC_CR_SW_RST(p_adc)                           (p_adc->CR |= (1UL<<27))  

/*! RW, Data expansion bit selection
 */
#define LL_ADC_CR_DATASIGN                                (1UL << 26)

/*! RW, Overrun interrupt enable
 */
#define LL_ADC_CR_OVR_IE                                  (1UL << 25)

/*! RW, DMA full interrupt enable
 */
#define LL_ADC_CR_DMA_FULL_IE                             (1UL << 23)

/*! RW, DMA half full interrupt enable
 */
#define LL_ADC_CR_DMA_HALF_IE                             (1UL << 22)

/*! RW, External trigger shift sample
 * After the trigger signal is generated, the clock cycle with a delay of N PCLK starts sampling again  
 * 0: not delay  
 * 1: 4   cycles  
 * 2: 16  cycles  
 * 3: 32  cycles  
 * 4: 64  cycles  
 * 5: 128 cycles  
 * 6: 256 cycles  
 * 7: 512 cycles  
 */
#define LL_ADC_CR_TRG_DLY(n)                              (((n)&0x7) << 19)

/*! RW, ADC scan channel order
 * The sequence of scan channels is set in a single - cycle scan or continuous scan direction mode  
 * 0: ADC channel selection registers are scanned in order from low to high  
 * 1: ADC channel selection registers are scanned in order from high to low  
 */
#define LL_ADC_CR_SCAN_DIR                                (1UL << 16)

/*! RW, Data alignment  
 * 0: left alignment 
 * 1: right alignment  
 */
#define LL_ADC_CR_ALIGN                                   (1UL << 11)

/*! RW, A/D conversion start (ADC start)  
 * There are two ways of placing ADST:  
 * 1.In single mode or single cycle mode, after the conversion, ADST will be automatically cleared by the hardware.  
 * 2.In continuous scan mode, A/D conversion will continue until the software writes 0 to the bit or the system reset.  
 * 1 = start of conversion  
 * 0 = end of transition or enter idle state  
 */
#define LL_ADC_CR_KST                                     (1UL << 8)

/*! RW, External trigger source selection  
 * 00: timer0 trigger  
 * 01: timer1 trigger  
 * 1x: timer4 trigger  
 */
#define LL_ADC_CR_TRG_SEL(n)                              (((n)&0x3) << 4)

/*! RW, Direct memory access enable  
 * 1 = DMA request enabled  
 * 0 = DMA disabled  
 */
#define LL_ADC_CR_DMA_EN                                  (1UL << 3)

/*! RW, External trigger enable  
 * 1 = start A/D conversion using an external trigger signal  
 * 0 = start A/D conversion without an external trigger signal  
 */
#define LL_ADC_CR_EXT_TRG_EN                              (1UL << 2)

/*! RW, A/D interrupt enable  
 * If ADINT is set, an interrupt request is generated at the end of A/D conversion  
 * 1 = enable A/D to be interrupted  
 * 0 = disable A/D interrup  
 */
#define LL_ADC_CR_IE                                      (1UL << 0)


/***** ADC_CHS Register *****/
/*! RW, In continuous scan mode, ADC input channel is enabled  
 * 1 = enabled  
 * 0 = disable  
 CHXEN<0>--PB0
 CHXEN<1>--PB1
 CHXEN<2>--PB2
 CHXEN<3>--PB3
 CHXEN<4>--PB4
 CHXEN<5>--PB5
 CHXEN<6>--PB6
 CHXEN<7>--PB7
 CHXEN<8>--PB8
 CHXEN<9>--PB9
 CHXEN<10>--PA0
 CHXEN<11>--PA1
 CHXEN<12>--PA2
 CHXEN<13>--PA3
 CHXEN<14>--PA4
 CHXEN<15>--PA5
 CHXEN<16>--PA6
 CHXEN<17>--PA7
 CHXEN<18>--PA8
 CHXEN<19>--PA9
 CHXEN<20>--PA10
 CHXEN<21>--PA11
 CHXEN<22>--PA12
 CHXEN<23>--PA13
 CHXEN<24>--PA14
 CHXEN<25>--PA15

 */
#define LL_ADC_CHS_EN(n)                                (((n)&0x3FFFFFF) << 0)

#define LL_ADC_CHS_0                     (1U << 0)   /*! ADC input channel 0  is PB0 */
#define LL_ADC_CHS_1                     (1U << 1)   /*! ADC input channel 1  is PB1 */
#define LL_ADC_CHS_2                     (1U << 2)   /*! ADC input channel 2  is PB2 */
#define LL_ADC_CHS_3                     (1U << 3)   /*! ADC input channel 3  is PB3 */
#define LL_ADC_CHS_4                     (1U << 4)   /*! ADC input channel 4  is PB4 */
#define LL_ADC_CHS_5                     (1U << 5)   /*! ADC input channel 5  is PB5 */
#define LL_ADC_CHS_6                     (1U << 6)   /*! ADC input channel 6  is PB6 */
#define LL_ADC_CHS_7                     (1U << 7)   /*! ADC input channel 7  is PB7 */
#define LL_ADC_CHS_8                     (1U << 8)   /*! ADC input channel 8  is PB8 */
#define LL_ADC_CHS_9                     (1U << 9)   /*! ADC input channel 9  is PB9 */
#define LL_ADC_CHS_10                    (1U << 10)  /*! ADC input channel 10 is PA0 */
#define LL_ADC_CHS_11                    (1U << 11)  /*! ADC input channel 11 is PA1 */
#define LL_ADC_CHS_12                    (1U << 12)  /*! ADC input channel 12 is PA2 */
#define LL_ADC_CHS_13                    (1U << 13)  /*! ADC input channel 13 is PA3 */
#define LL_ADC_CHS_14                    (1U << 14)  /*! ADC input channel 14 is PA4 */
#define LL_ADC_CHS_15                    (1U << 15)  /*! ADC input channel 15 is PA5 */
#define LL_ADC_CHS_16                    (1U << 16)  /*! ADC input channel 16 is PA6 */
#define LL_ADC_CHS_17                    (1U << 17)  /*! ADC input channel 17 is PA7 */
#define LL_ADC_CHS_18                    (1U << 18)  /*! ADC input channel 18 is PA8 */
#define LL_ADC_CHS_19                    (1U << 19)  /*! ADC input channel 19 is PA9 */
#define LL_ADC_CHS_20                    (1U << 20)  /*! ADC input channel 20 is PA10 */
#define LL_ADC_CHS_21                    (1U << 21)  /*! ADC input channel 21 is PA11 */
#define LL_ADC_CHS_22                    (1U << 22)  /*! ADC input channel 22 is PA12 */
#define LL_ADC_CHS_23                    (1U << 23)  /*! ADC input channel 23 is PA13 */
#define LL_ADC_CHS_24                    (1U << 24)  /*! ADC input channel 24 is PA14 */
#define LL_ADC_CHS_25                    (1U << 25)  /*! ADC input channel 25 is PA15 */


/***** ADC_STA Register *****/
/*! RC, DMA full pending, wirte 1 clear 0
 */
#define LL_ADC_STA_DMA_FULL_PEND                       (1UL << 11)

/*! RC, DMA half full pending, wirte 1 clear 0
 */
#define LL_ADC_STA_DMA_HALF_PEND                       (1UL << 10)

/*! RO, Current conversion channel  
 * When bit of BUSY is set 1, The six bits represent the channels in the transformation when BUSY = 1  
 * When bit of BUSY is set 0, The six bits represent the channels that can be converted next time  
 */
#define LL_ADC_STA_ADC_COVERSION_CHANNEL_GET(p_adc)       (((p_adc->STA)>>4) & 0x1F)

/*! RO, The A/D transition state(busy or idle)  
 * 0 = A/D converter is idle  
 * 1 = A/D converter is busy  
 */
#define LL_ADC_STA_BUSY                                (1UL << 2)

/*! RC, A/D Converts the end flag bit(write 1 to clear operation)  
 * This bit is set by the hardware at the end of the channel group conversion and cleared by the software  
 * 1 = A/D conversion is completed  
 * 0 = A/D conversion is incomplete  
 */
#define LL_ADC_STA_DONE                                (1UL << 0)


/***** ADC_DATA Register *****/
/*! RO, Valid flag  
 * 1 = DATA[11:0] bit DATA is valid  
 * 0 = DATA[11:0] bit DATA is invalid  
 * After the corresponding analog channel conversion is completed, this bit is set 1.  
 * The location bit is cleared by the hardware after reading the ADDATA register.  
 */
#define LL_ADC_DATA_ADC_VALID_IF_GET(p_adc)             (((p_adc->DATA)>>23) & 0x1)

/*! RO, Get data coverage flag  
 * 1 = DATA [11:0] DATA is overwritten  
 * 0 = DATA [11:0] DATA last conversion result  
 * Before the new transformation result is loaded into the register, if the DATA of DATA[15:0] is not read, the OVERRUN will set '1'  
 * After reading the ADDATA register, the bit is cleared by the hardware.  
 */
#define LL_ADC_DATA_ADC_OVERRUN_IF_GET(p_adc)           (((p_adc->DATA)>>22) & 0x1)

/*! RO, The 5 bits show the Channel selection corresponding to the current data  
 */
#define LL_ADC_DATA_ADC_CH_SEL_GET(p_adc)               (((p_adc->DATA)>>16) & 0x1F)

/*! RO, get 12 bit A/D conversion result
 */
#define LL_ADC_DATA_ADC_RESULT_GET(p_adc)               (((p_adc->DATA)>>0) & 0xFFFF)


/***** ADC_DMAADDR Register *****/
/*! RW, DMA start address.
 */
#define LL_ADC_DMAADDR_ADC_SET(n)                         (((n)&0xFFFFFFFF) << 0)


/***** ADC_DMACNT Register *****/
/*! RO, The length of data that has been dma completed
 */  
#define LL_ADC_DMACNT_DMA_CNT(n)                          (((n)&0x3FF) << 0)


/***** ADC_DMALEN Register *****/
/*! RW, The length of data that dma buffer
 */
#define LL_ADC_DMALEN_DMA_LEN(n)                          (((n)&0x3FF) << 0)

/***** ADC_OFFSET Register *****/
/*! RO, ADC compensation value OFFSET_ALL
 */
#define LL_ADC_ADC_OFFSET_ALL(n)                          (((n)&0x3F) << 24)

/*! RO, ADC compensation value OFFSET2
 */
#define LL_ADC_ADC_OFFSET2(n)                             (((n)&0x3F) << 16)

/*! RO, ADC compensation value OFFSET1
 */
#define LL_ADC_ADC_OFFSET1(n)                             (((n)&0x3F) << 8)

/*! RO, ADC compensation value OFFSET0
 */
#define LL_ADC_ADC_OFFSET0(n)                             (((n)&0x3F) << 0)

/**
  * @}
  */

/** @defgroup ADC_LL_Exported_Constants ADC LL Exported Constants
  * @ingroup  ADC_LL_Driver
  * @brief    ADC LL external constant definition
  *
@verbatim   
  ===============================================================================
                                Exported Constants
  ===============================================================================  
  
    Exported Constants mainly restricts the partial configuration of the abstraction 
    layer by using the form of enumeration to facilitate the use and understanding of 
    the module configuration. For the specific enumeration meaning, please refer to 
    the annotation of each module.

@endverbatim
  *
  * @{
  */
  
/***** DRIVER API *****/



/***** LL API *****/

/**
  * @brief Enumeration constant for low layer ADC scan direction
  */
typedef enum {
    /*! ADC data scan bit is from low to high
     */
    LL_ADC_SCAN_DIR_L2H         = 0,
    /*! ADC data scan bit is from high to low
     */
    LL_ADC_SCAN_DIR_H2L,
} TYPE_ENUM_LL_ADC_SCAN_DIR;

/**
  * @brief Enumeration constant for low layer ADC data align mode
  */
typedef enum {
    /*! ADC data is left align
     */
    LL_ADC_DATA_LEFT_ALIGN      = 0,
    /*! ADC data is right align
     */
    LL_ADC_DATA_RIGHT_ALIGN,
} TYPE_ENUM_LL_ADC_DATA_ALIGN;

/**
  * @brief Enumeration constant for low layer ADC scan mode
  */
typedef enum {
    /*! sampling starts again after delaying the clock cycle of 0 PCLK
     */
    LL_ADC_NO_DELAY             = 0,
    /*! sampling starts again after delaying the clock cycle of 4 PCLK
     */
    LL_ADC_DELAY_4_clock        = 1,
    /*! sampling starts again after delaying the clock cycle of 16 PCLK
     */
    LL_ADC_DELAY_16_clock       = 2,
    /*! sampling starts again after delaying the clock cycle of 32 PCLK
     */
    LL_ADC_DELAY_32_clock       = 3,
    /*! sampling starts again after delaying the clock cycle of 64 PCLK
     */
    LL_ADC_DELAY_64_clock       = 4,
    /*! sampling starts again after delaying the clock cycle of 128 PCLK
     */
    LL_ADC_DELAY_128_clock      = 5,
    /*! sampling starts again after delaying the clock cycle of 256 PCLK
     */
    LL_ADC_DELAY_256_clock      = 6,
    /*! sampling starts again after delaying the clock cycle of 512 PCLK
     */
    LL_ADC_DELAY_512_clock      = 7,
} TYPE_ENUM_LL_ADC_TRG_SHIFT;

/**
  * @brief Enumeration constant for low layer ADC state
  */
typedef enum {
    /*! ADC  conversion  over
     */
    LL_ADC_CONVERSION_OVER      = 0,
    /*! ADC start of conversion
     */
    LL_ADC_ADLE_STATE           = 1,
    
} TYPE_ENUM_LL_ADC_ADST;

/**
  * @brief Enumeration constant for low layer ADC state
  */
typedef enum {
    /*! ADC  VSEL  VCC
     */
    LL_ADC_VSEL_2V              = 0,
    /*! ADC  VSEL  VREF
     */
    LL_ADC_VSEL_2_5V            = 1,
    /*! ADC  VSEL  VCC
     */
    LL_ADC_VSEL_4_5V            = 2,
    /*! ADC  VSEL  VREF
     */
    LL_ADC_VSEL_AVCC            = 3,
} TYPE_ENUM_LL_ADC_VSEL;

/**
  * @brief Enumeration constant for low layer ADC state
  */
typedef enum {
    /*! ADC  VSEL  VCC
     */
    LL_ADC_VCC_VOLTAGE_5V       = 0,
    /*! ADC  VSEL  VREF
     */
    LL_ADC_VCC_VOLTAGE_3_3V     = 1,
} TYPE_ENUM_LL_ADC_VCC_VOLAGE;

/**
  * @brief Enumeration constant for low layer ADC trgsel
  */
typedef enum {
    /*! ADC TRG SOURCE is TIMER_0
     */
    LL_ADC_TRG_TIMER_0          = 0,
    /*! ADC TRG SOURCE is TIMER_1
     */
    LL_ADC_TRG_TIMER_1          = 1,
    /*! ADC TRG SOURCE is TIMER_4
     */
    LL_ADC_TRG_TIMER_4          = 2,
} TYPE_ENUM_LL_ADC_TRG_SEL;


/**
  * @brief Enumeration constant for low layer ADC state
    ADC_BOUND0 = 0.5 / ADC_VREF * 4096
    ADC_BOUND1 = (ADC_VREF-0.7) / ADC_VREF *4096
  */
typedef enum {
    LL_ADC_BOUND_VSEL_2V              = 0x0a660400,

    LL_ADC_BOUND_VSEL_2_5V            = 0x0b850333,

    LL_ADC_BOUND_VSEL_4_5V            = 0x0d8201c7,

    LL_ADC_BOUND_VSEL_5_0V            = 0x0dc20199,

    LL_ADC_BOUND_VSEL_3_3V            = 0x0c9b026c,
    
} TYPE_ENUM_LL_ADC_BOUND;

/***** LL API AND DRIVER API *****/


/**
  * @}
  */

/** @defgroup ADC_LL_Exported_Struct ADC LL Exported Struct
  * @ingroup  ADC_LL_Driver
  * @brief    ADC LL external configuration structure definition
  *
@verbatim   
  ===============================================================================
                                Exported Struct
  ===============================================================================  

    Exported Struct mainly extracts the ADC registers from the API, and abstracts 
    the structure. As long as it implements the low coupling between the registers 
    and the registers, the user only needs to configure the structure of the abstraction 
    layer and call hal_adc_init. Function, you can configure the ADC module without 
    involving the configuration of the collective register.

@endverbatim
  *
  * @{
  */

/**
  * @brief Low layer ADC initialization structure 
  */
typedef struct __ll_adc_cfg{
    
    /*! ADC vcc voltage selection
     */
    TYPE_ENUM_LL_ADC_VCC_VOLAGE         vcc_voltage;
    /*! ADC reference voltage selection
     */
    TYPE_ENUM_LL_ADC_VSEL               ref_voltage;
    /*! ADC data align
     */
    TYPE_ENUM_LL_ADC_DATA_ALIGN         data_align;
    /*! ADC scan direction
     */
    TYPE_ENUM_LL_ADC_SCAN_DIR           scan_direction;
    /*! ADC prescaler value
     */
    u8                                  prescaler;
    /*! ADC Interval time period between two consecutive samples (n*ADCCLK)
     */
    u8                                  interval_period;
    /*! ADC channel selection
     */
    u32                                 channel_map;
    /*! ADC dma buff addr
     */
    u32                                 dma_addr;
    /*! ADC dma buff len
     */
    u16                                 dma_len;
}TYPE_LL_ADC_INIT;

/**
  * @brief Low layer ADC External trigger Configure the structure 
  */
typedef struct __ll_adc_ext_trg_cfg{
    /*! ADC External trigger source selection
     */
    TYPE_ENUM_LL_ADC_TRG_SEL            ext_trg_source;
    /*! ADC After the trigger signal is generated, the sampling starts again after delaying the clock cycle of N PCLK
     */
    TYPE_ENUM_LL_ADC_TRG_SHIFT          ext_trg_delay;
}TYPE_LL_ADC_EXT_TRG_CONFIG;


/**
  * @}
  */

/** @defgroup ADC_LL_Interrupt ADC LL Interrupt Handle function
  * @brief   ADC LL Interrupt Handle function
  *
@verbatim   
  ===============================================================================
                        Interrupt Handle function
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the ADC  
    Interrupt Handle function.

    how to use?

    The ADC interrupt handler uses a callback method that reserves the interface 
    to the user in the form of a callback function. The client needs to initialize 
    the callback function when initializing the ADC in order for the interrupt to 
    be processed normally. 
   
@endverbatim
  *
  * @{
  */



/**
  * @}
  */
  
/** @defgroup ADC_LL_Inti_Cfg ADC LL Initialization And Configuration
  * @brief    ADC LL Initialization And Configuration
  *
@verbatim   
  ===============================================================================
                        Initialization And Configuration
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the ADC data 
    Initialization and Configuration.
    
    how to use?

@endverbatim
  *
  * @{
  */

/**
  * @brief  Low layer adc once mode init function
  * @param  p_adc: ponit of adc
  * @param  p_init : Configure the adc initialization structure
  * @retval None
  */
void ll_adc_once_init(ADC_TypeDef *p_adc, TYPE_LL_ADC_INIT *p_init);

/**
  * @brief  Low layer adc init function
  * @param  p_adc: ponit of adc
  * @param  p_init : Configure the p_timer initialization structure
  * @retval None
  */
void ll_adc_init(ADC_TypeDef *p_adc, TYPE_LL_ADC_INIT *p_init);

/**
  * @brief  Low layer adc External trigger config function
  * @param  p_adc: ponit of adc
  * @param  p_init : External trigger Configure the structure
  * @retval None
  */
void ll_adc_external_trigger_config(ADC_TypeDef *p_adc, TYPE_LL_ADC_EXT_TRG_CONFIG *p_init);

/**
  * @brief  Low layer adc set channel map function
  * @param  channel: channel map
  * @retval None
  */
void ll_adc_set_channel_map(u32 channel);

/**
  * @brief  Low layer adc set dma addr function
  * @param  addr: dma addr
  * @retval None
  */
void ll_adc_set_dma_addr(u32 addr);

/**
  * @}
  */
  
/** @defgroup ADC_LL_Data_Transfers ADC LL Data transfers functions
  * @brief    ADC LL Data transfers functions 
  *
@verbatim   
  ===============================================================================
                            Data transfers functions
  ===============================================================================  

    This subsection provides a set of functions allowing to manage the ADC data 
    transfers and receive.
  
@endverbatim
  *
  * @{
  */

/**
  * @brief  Low layer adc interrupt enable function
  * @param  None
  * @retval None
  */
void ll_adc_interrupt_enable(void);

/**
  * @brief  Low layer adc interrupt disable function
  * @param  None
  * @retval None
  */
void ll_adc_interrupt_disable(void);

/**
  * @brief  Low layer adc interrupt get function
  * @param  None
  * @retval result
  */
#define LL_ADC_INTERRUPT_GET()                              (ADC->CR & LL_ADC_CR_ADC_IE)

/**
  * @brief  Low layer adc over run interrupt enable function
  * @param  None
  * @retval None
  */
void ll_adc_ovr_interrupt_enable(void);

/**
  * @brief  Low layer adc over run interrupt disable function
  * @param  None
  * @retval None
  */
void ll_adc_ovr_interrupt_disable(void);

/**
  * @brief  Low layer adc over run interrupt get function
  * @param  None
  * @retval result
  */
#define LL_ADC_OVR_INTERRUPT_GET()                          (ADC->CR & LL_ADC_CR_OVR_IE)

/**
  * @brief  Low layer adc dma full interrupt enable function
  * @param  None
  * @retval None
  */
void ll_adc_dma_full_interrupt_enable(void);

/**
  * @brief  Low layer adc dma full interrupt disable function
  * @param  None
  * @retval None
  */
void ll_adc_dma_full_interrupt_disable(void);

/**
  * @brief  Low layer adc dma full interrupt get function
  * @param  None
  * @retval result
  */
#define LL_ADC_DMA_FULL_INTERRUPT_GET()                     (ADC->CR & LL_ADC_CR_DMA_FULL_IE)

/**
  * @brief  Low layer adc dma half full interrupt enable function
  * @param  None
  * @retval None
  */
void ll_adc_dma_half_full_interrupt_enable(void);
/**
  * @brief  Low layer adc dma half full interrupt disable function
  * @param  None
  * @retval None
  */
void ll_adc_dma_half_full_interrupt_disable(void);
/**
  * @brief  Low layer adc dma half full interrupt get function
  * @param  None
  * @retval result
  */
#define LL_ADC_DMA_HALF_INTERRUPT_GET()                     (ADC->CR & LL_ADC_CR_DMA_HALF_IE)

/**
  * @brief  Low layer adc enable function
  * @param  None
  * @retval None
  */
void ll_adc_enable(void);
/**
  * @brief  Low layer adc disable function
  * @param  None
  * @retval None
  */
void ll_adc_disable(void);
/**
  * @brief  Low layer adc enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_EN_GET()                                     (ADC->CFG & LL_ADC_CFG_ADC_EN)

/**
  * @brief  Low layer adc ldo enable function
  * @param  None
  * @retval None
  */
void ll_adc_ldo_enable(void);
/**
  * @brief  Low layer adc ldo disable function
  * @param  None
  * @retval None
  */
void ll_adc_ldo_disable(void);
/**
  * @brief  Low layer adc enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_LDO_EN_GET()                                 (ADC->CFG & LL_ADC_CFG_LDO_EN)

/**
  * @brief  Low layer adc hardware data calibrate enable function
  * @param  None
  * @retval None
  */
void ll_adc_hardword_calibrate_enable(void);
/**
  * @brief  Low layer adc hardware data calibrate disable function
  * @param  None
  * @retval None
  */
void ll_adc_hardword_calibrate_disable(void);
/**
  * @brief  Low layer hardware data calibrate enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_HARDWARE_CAL_EN_GET()                        (ADC->CR & LL_ADC_CR_CAL_EN)

/**
  * @brief  Low layer adc dma enable function
  * @param  None
  * @retval None
  */
void ll_adc_dma_enable(void);
/**
  * @brief  Low layer adc dma disable function
  * @param  None
  * @retval None
  */
void ll_adc_dma_disable(void);
/**
  * @brief  Low layer adc dma enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_DMA_EN_GET()                                 (ADC->CR & LL_ADC_CR_DMA_EN)

/**
  * @brief  Low layer adc external interrupt source enable function
  * @param  None
  * @retval None
  */
void ll_adc_ext_trg_src_enable(void);
/**
  * @brief  Low layer adc external interrupt source disable function
  * @param  None
  * @retval None
  */
void ll_adc_ext_trg_src_disable(void);
/**
  * @brief  Low layer adc external interrupt source enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_EXT_TRG_SRC_EN_GET()                         (ADC->CR & LL_ADC_CR_EXT_TRG_EN)

/**
  * @brief  Low layer adc start enable function
  * @param  None
  * @retval None
  */
void ll_adc_start_enable(void);
/**
  * @brief  Low layer adc start disable function
  * @param  None
  * @retval None
  */
void ll_adc_start_disable(void);
/**
  * @brief  Low layer adc start enable get
  * @param  None
  * @retval result
  */
#define LL_ADC_START_EN_GET()                               (ADC->CR & LL_ADC_CR_KST)

/**
  * @brief  Low layer adc done pending get function
  * @param  None
  * @retval value
  */
#define LL_ADC_DONE_PEND_GET()                              (ADC->STA & LL_ADC_STA_DONE)
/**
  * @brief  Low layer adc done pending clear function
  * @param  None
  * @retval None
  */
#define LL_ADC_DONE_PEND_CLR()                              (ADC->STA = LL_ADC_STA_DONE)

/**
  * @brief  Low layer dma full pending get function
  * @param  None
  * @retval value
  */
#define LL_ADC_DMA_FULL_PEND_GET()                          (ADC->STA & LL_ADC_STA_DMA_FULL_PEND)
/**
  * @brief  Low layer dma full pending clear function
  * @param  None
  * @retval None
  */
#define LL_ADC_DMA_FULL_PEND_CLR()                          (ADC->STA = LL_ADC_STA_DMA_FULL_PEND)

/**
  * @brief  Low layer dma half full pending get function
  * @param  None
  * @retval value
  */
#define LL_ADC_DMA_HALF_PEND_GET()                          (ADC->STA & LL_ADC_STA_DMA_HALF_PEND)
/**
  * @brief  Low layer dma half full pending clear function
  * @param  None
  * @retval None
  */
#define LL_ADC_DMA_HALF_PEND_CLR()                          (ADC->STA = LL_ADC_STA_DMA_HALF_PEND)

/**
  * @brief  ADC compensation value OFFSET_ALL get function
  * @param  None
  * @retval None
  */
#define LL_ADC_OFFSET_ALL_GET()                             ((ADC->OFFSET>>24) & 0x3f)

/**
  * @brief  ADC compensation value OFFSET2 get function
  * @param  None
  * @retval None
  */
#define LL_ADC_OFFSET2_GET()                                ((ADC->OFFSET>>16) & 0x3f)

/**
  * @brief  ADC compensation value OFFSET1 get function
  * @param  None
  * @retval None
  */
#define LL_ADC_OFFSET1_GET()                                ((ADC->OFFSET>>8) & 0x3f)

/**
  * @brief  ADC compensation value OFFSET0 get function
  * @param  None
  * @retval None
  */
#define LL_ADC_OFFSET0_GET()                                ((ADC->OFFSET>>0) & 0x3f)


/**
  * @brief  Low layer adc config
  * @param  ext_trg_source: Enumeration constant for low layer ADC trgsel
  * @param  ext_trg_delay: Enumeration constant for low layer ADC scan mode
  * @retval None
  */
void ll_adc_trgsel_config( TYPE_ENUM_LL_ADC_TRG_SEL ext_trg_source,  TYPE_ENUM_LL_ADC_TRG_SHIFT ext_trg_delay);
/**
  * @brief  Low layer adc config
  * @param  ref_vol: Select ADC reference voltage 
  * @retval None
  */
void ll_adc_config(TYPE_ENUM_LL_ADC_VSEL ref_vol);
/**
  * @brief  Low layer adc config
  * @param  ref_vol: Select ADC reference voltage 
  * @param  channel_map: channel bit map (ex:LL_ADC_CHS_0--LL_ADC_CHS_25) 
  * @param  dma_addr: Select ADC dma address 
  * @retval None
  */
void ll_adc_multi_config(TYPE_ENUM_LL_ADC_VSEL ref_vol, u32 channel_map, u16* dma_addr);
/**
  * @brief  Adc data get
  * @param  None
  * @retval None
  */
void ll_adc_data_get(void);

/**
  * @brief  Get adc channel sample result 
  * @param  adc_channel: ADC input channel enable
  * @retval None
  */
u16 ll_adc_channel_sample_get(u32  adc_channel);

/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif

/**
  * @}
  */

/**
  * @}
  */

#endif //__TS32F020D_LL_ADC_H

/*************************** (C) COPYRIGHT 2022 JUSHENG ***** END OF FILE *****/
